1.. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacturing programmable memory devices. More particularly, this invention relates to an improved circuit configuration and method for manufacturing a one-time programmable (OTP) memory cells.
2.. Description of the Relevant Art
The need for precision power management products and circuits are increasing with reduction in power supply voltage and higher frequency of operation. Band-gap circuits, output voltage and frequency need precise control in modem power circuits. In the past, the precise control was obtained by using wafer level trim techniques such as metal/poly fuses and forward/reverse trimming of Zener diodes. However, often wafer trim techniques are not sufficient to maintain the precision even after the chip is packaged due to the additional stress and charges induced by the package. Due to this reason, there is a need for post package trimming using one-time programmable devices.
Most prior art post package trim techniques use an NMOSFET with a floating gate that is coupled to the control gate through a coupling capacitor. FIG. 1A shows a double poly stacked gate structure where the partial overlap of floating gate and control gate forms the coupling capacitor. The operational principle is to collect electrons in the floating gate and shift the threshold voltage of the NMOSFET. The electrons are collected using different techniques such as Fowler-Nordheim tunneling and HCI hot carrier injection. To improve the tunneling efficiency and lower the trimming voltage, different techniques are applied to enhance the electrical field in the carrier injection region. FIG. 1B shows another stacked gate structure where a portion of floating gate oxide is thinned to improve electron-collecting capability. However the removal of partial gate oxide requires extra etching step therefore increases the cost.
One-time programmable devices for post package trimming usually are processed at the same time as the functional circuit using standard CMOS technologies. For improving the hot-carrier degradation in the mainstream sub-micron CMOS technologies, a sidewall spacer with lightly doped drain (LDD) implant is used to reduce the drain to substrate field at the drain end of the channel. However, in order to increase the efficiency of electron injection into the floating gate of an NMOS, a higher drain field becomes necessary. FIGS. 2A and 2B are two cross sectional views for illustrating the configurations of another conventional OTP memory cells structure form by single poly process where FIG. 2A is the floating gate NMOS and FIG. 2B is the coupling capacitor using PMOS. As that shown in FIG. 2A, prior art structures use a deep heavily doped N region in the drain region to increase the electrical field at the drain region. The low concentration N-dopant LDD is wiped out due to the high dopant concentration of the deep N doped region and this increases the electric field at the drain junction. The floating gate is coupled to the control gate through a P-MOS capacitor as shown in FIG. 2B. The coupling ratio between the NMOS gate capacitance and the coupling capacitor determines how much voltage that is presented on the floating gate when compared to the voltage applied on the control gate. Typically, the coupling ratio is about 6. to 10, thus the coupling capacitor is six to ten times higher than the NMOS gate capacitance. During the process of programming a drain voltage for applying to the NMOS and a high gate voltage is applied to the control gate to collect the hot electrons or tunnel electrons flowing in the high field region of the NMOS drain region. A higher threshold on the NMOS implies that the electrons have been collected in the floating gate. Although the application of deep N region wipe out the LDD region therefore increase the electrical field at the drain region, the voltage applied to control gate for programming still not low enough for many applications that require fast programming.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved OTP manufacturing processes and configuration that can overcome the difficulties generated by the LDD difficulties. Furthermore, a simplified configuration is also required to reduce the manufacturing complexities to achieve lower production cost and meanwhile increase the production yield while providing device with improved performance and reliability.